1. Field of the Invention
The present invention relates generally to a semiconductor device and fabrication method thereof. More specifically, the present invention is directed to a method of fabricating a hetero bipolar transistor.
2. Description of the Related Art
Recently, with a view to improving high-frequency performance, the development of hetero bipolar transistors (HBTs), comprising a bipolar transistor formed on a silicon substrate and a Si/SiGe heterojunction structure incorporated into the bipolar transistor, has been accelerated.
A typical HBT of the type mentioned above comprises material having a great affinity to the general-purpose silicon process (Si substrate and SiGe layer), thereby offering significant advantages such as high integration and cost reduction. Additionally, formation and integration of an HBT and a MOS transistor (MOSFET) on a common Si substrate makes it possible to fabricate a high-performance BiCMOS device. Such a BiCMOS device has promise as a system LSI capable of finding applications in the field of communication-related technology.
Various proposals for HBTs of the Si/Si1-xGex type have been made.
An example of conventional Si/Si1-xGex type HBTs is set forth in Japanese Patent Kokai Publication No. (2000)332025.
FIGS. 6-9 are views illustrating in cross section a structure of a conventional Si/Si1-xGex type HBT.
As shown in FIG. 9, an upper portion of an Si substrate 500 whose principle plane is (001) is a retrograde well 501 which is 1 μm deep and which contains N-type impurities (e.g., phosphor) introduced by means of epitaxial growth, ion implantation, or the like. It is controlled such that a region in the vicinity of a surface of the Si substrate 500 is doped with N-type impurities at a concentration of approximately 1×1017 atoms·cm−3. Additionally, a shallow trench 503 filled up with silicon dioxide and a deep trench 504 comprising an undoped polysilicon film 505 and a silicon oxide film 506 surrounding the undoped polysilicon film 505 are formed each serving as isolation. The trench 503 is approximately 0.35 μm deep. The trench 504 is approximately 2 μm deep.
A collector layer 502 is formed in a region sandwiched between trenches 503 in the Si substrate 500. On the other hand, an N+ collector extraction layer 507, for establishing contact with an electrode of the collector layer 502 via the retrograde well 501, is formed in a region of the substrate that is isolated from the collector layer 502 by the shallow trench 503.
Additionally, a first deposition oxide film 508 (approximately 30 nm thick) provided with a collector opening portion 510 is formed on the Si substrate 500. And, a polysilicon layer 509 is formed overlying the first deposition oxide film 508. An Si/Si1-xGex layer 511, which is a laminated layer of an Si1-xGex layer (approximately 60 nm thick) doped with P-type impurities and an Si film (approximately 10 nm), is formed on a portion of an upper surface of the silicon substrate 500 exposed to the collector opening portion 510. The Si/Si1-xGex layer 511 extends onto the polysilicon layer 509 from the entire surface of the Si substrate 500 exposed to the collector opening portion 510.
A central lower portion of the Si/Si1-xGex layer 511 serves as an internal base 519. On the other hand, a central upper portion of the Si/Si1-xGex layer 511 serves as an emitter layer.
Most of the Si1-xGex layer of the Si/Si1-xGex layer 511 is doped with P-type impurities such as boron (B) at approximately 2×1018 atoms·cm−3. On the other hand, the Si layer is doped by diffusion of N-type impurities (e.g., phosphor) from an N+ polysilicon layer 529 with a concentration ranging from approximately 1×1020 atoms·cm−3 to approximately 1×1017 atoms·cm−3 in the direction of the depth of the substrate.
Here, it is arranged such that the edge of the shallow trench 503 is situated interior to the edge of the collector opening portion 510. As a result of such arrangement, the shallow trench 503 is located on the inward side, thereby making it possible to reduce the gross area of an HBT. However, in the case where the active region/isolation junction part Rai gets into a carrier movement region of the HBT, this causes concern for the influence of such intrusion, for example, the occurrence of a defect by stress.
A second deposition oxide film 512 (approximately 30 nm thick) is formed, as an etching stopper, on the Si/Si1-xGex layer 511. The second deposition oxide film 512 is provided with a base junction opening portion 514 and a base opening portion 518. The outside width, A, of the second deposition oxide film 512 around the base opening portion 518 is as shown in FIG. 7.
A P+ polysilicon layer 515 (approximately 150 nm thick) filling up the base junction opening portion 514 and extending on the second deposition oxide film 512, and a third deposition oxide film 517 are formed. An extrinsic base 516 is made up of a portion of the Si/Si1-xGex layer 511 other than a region thereof located beneath the base opening portion 518, and the P+ polysilicon layer 515.
Of the P+ polysilicon layer 515 and the third deposition oxide film 517, their portions located above the base opening portion 518 of the second deposition oxide film 512 are opened. A fourth deposition oxide film 520 (approximately 30 nm thick) is formed on a side surface of the P+ polysilicon layer 515. Additionally, a polysilicon sidewall 521 (approximately 100 nm thick) is formed overlying the fourth deposition oxide film 520. And, an N+ polysilicon layer 529 filling up the base opening portion 518 and extending on the third deposition oxide film 517 is formed. The N+ polysilicon layer 529 serves as an emitter extraction electrode. The P+ polysilicon layer 515 and the N+ polysilicon layer 529 are electrically isolated one from the other by the fourth deposition oxide film 520, and diffusion of impurities from the P+ polysilicon layer 515 into the N+ polysilicon layer 529 is prevented from occurring. Furthermore, an upper surface of the P+ polysilicon layer 515 and the N+ polysilicon layer 529 are isolated one from the other by the third deposition oxide film 517. In addition, outer side surfaces of the N+ polysilicon layer 529 and the P+ polysilicon layer 515 are covered with a sidewall 523.
Furthermore, Ti silicide layers 524 are formed respectively on surfaces of the collector extraction layer 507, the P+ polysilicon layer 515, and the N+ polysilicon layer 529.
In addition to the above, the entire substrate is covered with an interlayer dielectric 525. Connecting holes are formed passing completely through the interlayer dielectric 525 and extending to the Ti silicide layers 524 on the N+ collector extraction layer 507, the P+ polysilicon layer 515 which is a part of the extrinsic base, and the N+ polysilicon layer 529 which is an emitter extraction electrode, respectively. And, W plugs 526 with which the connecting holes are filled up, and metallic wires 527 connected to the W plugs 526 and extending on the interlayer dielectric 525 are formed.
A process of the fabrication of a conventional HBT will now be described with reference to FIGS. 6-9.
In the first place, in the step of FIG. 6(a), an N-type retrograde well 501 which is approximately 1 μm deep is formed either by epitaxial growth of an Si monocrystal layer upon an upper portion of an Si substrate 500 whose principal plane is (001) while performing a doping process with N-type impurities, or by performing high-energy ion implantation after epitaxial growth. Alternatively, it is possible to form such a retrograde well 501 by implanting ions into a part of the Si substrate 500 without epitaxial growth. In this case, it is controlled such that in the formation of the HBT a region in the vicinity of the surface of the Si substrate 500 is doped with N-type impurities at approximately 1×1017 atoms·cm−3 because such a region becomes a collector layer of the HBT.
Then, a shallow trench 503 filled up with silicon dioxide, and a deep trench 504 made up of an undoped polysilicon film 505 and a silicon oxide film 506 surrounding the undoped polysilicon film 505 are formed, each serving as the isolation. The trench 503 is approximately 0.35 μm deep. The trench 504 is approximately 2 μm deep. A region sandwiched between shallow trenches 503 in the Si substrate 500 becomes a collector layer 502. Additionally, an N+ collector extraction layer 507 for establishing contact with a collector electrode is formed in a region of the Si substrate 500 isolated from the collector layer 502 by the shallow trench 503.
Next, in the step of FIG. 6(b), a chemical vapor deposition (CVD) treatment using tetraethyl orthosilicate (TEOS) and oxygen is carried out at a processing temperature of 680 degrees Centigrade, for formation of a first deposition oxide film 508 (approximately 30 nm thick) on the wafer. Subsequently, a polysilicon layer 509 (approximately 50 nm thick) is formed on the first deposition oxide film 508. Thereafter, the polysilicon layer 509 is patterned by means of dry etching or the like. This is followed by removal of the first deposition oxide film 508 by means of wet etching using hydrofluoric acid or the like, for formation of a collector opening portion 510.
Next, in the step of FIG. 6(c), the wafer is subjected to a UHV-CVD (Ultrahigh Vacuum Chemical Vapor Deposition) treatment and, as a result, an Si1-xGex layer (approximately 60 nm thick) is grown epitaxially all over a surface area of the Si substrate 500 exposed to the collector opening portion 510 and a surface of the polysilicon layer 509. And, after completion of the formation of the Si1-xGex layer, an Si layer (approximately 10 nm thick) is epitaxially grown upon the Si1-xGex layer. These layers, i.e., the Si1-xGex and Si layers, together constitute an Si/Si1-xGex layer 511. Here, the Si1-xGex layer is of the P type because of introduction of boron (B) thereinto. The boron density is 2×1018 atoms·cm−3. At this time, it is arranged such that the Si layer remains undoped.
On the Si1-xGex layer, a monocrystal Si layer is formed in the collector opening portion 510 and a polycrystal Si layer is formed above the polysilicon layer 509.
Next, in the step of FIG. 7(d), a second deposition oxide film 512 (30 nm thick), which will serve as an etching stopper, is formed on the wafer. Thereafter, the second deposition oxide film 512 is patterned by means of wet etching using a resist mask Re2 formed on the second deposition oxide film 512, for formation of a base junction opening portion 514. This is followed by removal of the resist mask Re2 by means of both ashing and cleaning employing a mixed liquid of sulfuric acid, oxygenated water, and water.
Next, in the step of FIG. 7(e), a P+ polysilicon layer 515 (approximately 150 nm thick and heavily doped to above 1×1020 atoms·cm−3) is deposited on the wafer by means of CVD. Then, a third deposition oxide film 517 (approximately 100 nm thick) is deposited.
Next, the third deposition oxide film 517 and the P+ polysilicon layer 515 are patterned such that a base opening portion 518 is formed centrally in the third deposition oxide film 517 and the P+ polysilicon layer 515. This base opening portion 518 reaches the second deposition oxide film 512. The base opening portion 518 is smaller in size than a central portion of the second deposition oxide film 512, so that the base opening portion 518 will not spread over the base junction opening portion 514. As the result of the FIG. 7(e) step, an extrinsic base 516 is formed by the P+ polysilicon layer 515 and a portion of the Si/Si1-xGex layer 511 other than its central portion.
Next, in the step of FIG. 7(f), a fourth deposition oxide film 520 (approximately 30 nm thick) and a polysilicon film (approximately 150 nm thick) are deposited all over the wafer by means of CVD. And, the polysilicon film is etched back by means of anisotropic dry etching in such a way that a side wall 521 of polysilicon is formed on side surfaces of the P+ polysilicon layer 515 and the third deposition oxide film 517 with the fourth deposition oxide film 520 disposed between the side wall 521 and the P+ polysilicon layer 515 and the third deposition oxide film 517. Next, exposed portions of the second deposition oxide film 512 and the fourth deposition oxide film 520 are removed by means of wet etching using hydrofluoric acid or the like. At this time, an upper layer of the Si/Si1-xGex layer 511, i.e., the Si layer, is exposed in the base opening portion 518. Additionally, since wet etching is an isotropic etching process, this causes the second deposition oxide film 512 and the fourth deposition oxide film 520 to be etched laterally and, as a result, the size of the base opening portion 518 is increased. Stated another way, the width, W1, of the base opening portion 518 is determined by the amount of wet etching.
Next, in the step of FIG. 8(g), an N+ polysilicon layer 529 (approximately 250 nm thick) is deposited on the wafer. Thereafter, the N+ polysilicon layer 529 and the third deposition oxide film 517 are patterned by means of dry etching to form an emitter extraction electrode.
Next, in the step of FIG. 8(h), the P+ polysilicon layer 515, the second deposition oxide film 512, the Si/Si1-xGex layer 511, and the polysilicon layer 509 are patterned by means of dry etching, to determine the shape of the extrinsic base 516.
Next, in the step of FIG. 8(i), a deposition oxide film (approximately 120 nm thick) is formed on the wafer. Then, a dry etching treatment is carried out to form a side wall 523 on side surfaces of the N+ polysilicon layer 529 and the P+ polysilicon layer 515.
An exposed portion of the first deposition oxide film 508 is removed by means of the dry etching (over-etching) so that surface portions of the N+ polysilicon layer 529, the P+ polysilicon layer 515, and the N+ collector extraction layer 507 are exposed.
Further, the following processing will be carried out. In the first place, an approximately 40-nm thick Ti film is deposited all over the wafer by means of sputtering. Thereafter, an RTA (rapid thermal anneal) process is carried out at 675 degrees Centigrade for 30 seconds to form Ti silicide layers 524 on the exposed surface portions of the N+ polysilicon layer 529, the P+ polysilicon layer 515, and the N+ collector extraction layer 507, respectively. Thereafter, a portion of the Ti film remaining not reacted is selectively removed. Then, in order to change the crystal structure of the Ti silicide layer 524, annealing is carried out.
Next, an interlayer dielectric 525 is formed all over the wafer. This is followed by formation of connecting holes which pass completely through the interlayer dielectric 525 and then extend to the Ti silicide layers 524 on the N+ polysilicon layer 529, the P+ polysilicon layer 515, and the N+ collector extraction layer 507, respectively. And, each connecting hole is filled up with a W film to form a W plug 526. This is followed by deposition of a film of aluminum alloy all over the wafer. The aluminum alloy film is patterned to form a metallic wire 527 connected to each W plug 526 and extending on the interlayer dielectric 525.
As the result of the above-described steps, an HBT having a structure as illustrated in FIG. 9, i.e., an HBT provided with a collector made of N-type Si, a base made of the P+ type Si/Si1-xGex layer 511, and an emitter made of N+ Si, is now fabricated. In addition, because of diffusion of high-concentration N-type impurities such as phosphorous into the Si layer of the Si/Si1-xGex layer 511 of the HBT from the N+ polysilicon layer 529, the Si layer becomes an N+ type Si layer.
Incidentally, in the fabrication of the above-described conventional Si/Si1-xGex HBT, in order to perform a pattering treatment with a high degree of accuracy, dry etching is employed in principle as an etching method since dry etching is superior in controllability because of its anisotropic properties. However, the Si/Si1-xGex layer 511 is susceptible to damage when subjected to dry etching. To cope with this problem, the second deposition oxide film 512 is formed, as an etching stopper layer, directly above the Si/Si1-xGex layer 511 and, at the time of removal of the second deposition oxide film 512, wet etching is employed since it causes less damage to the Si/Si1-xGex layer 511. More specifically, in the fabrication step of forming the base junction opening portion as illustrated in the FIG. 7(d), at the time of pattering the second deposition oxide film 512, wet etching is employed.
However, the wet etching is an isotropic etching process, which means that the second deposition oxide film 512 is etched also in a lateral direction. As the result of this, the outside width, A, of the second deposition oxide film 512 around the base opening portion 518 is diminished. Besides, since there is entrance of etching liquid from an interface between the resist Re2 and the second deposition oxide film 512, this reduces the thickness of the second deposition oxide film 512. At the same time, such etching liquid entrance accelerates the rate of the above-mentioned lateral etching. And, if the thickness of the second deposition oxide film 512 is reduced excessively, the effect of the second deposition oxide film 512 as an etching stopper at the time of forming the base opening portion 518 will wear off.
Meanwhile, recently micro-fabrication has been demanded in the field of Si/Si1-xGex type HBT technology. With the advancement of the HBT micro-fabrication, it is required that the amount of lateral etching to the second deposition oxide film 512 be held low.
In the above-mentioned conventional technology, however, the deposition oxide film 512 is etched laterally and the thickness of the deposition oxide film 512 is reduced, therefore producing inconvenience that the degree of micro-fabrication is limited.
In other words, in order to perform micro-fabrication on the deposition oxide film 512 with high controllability, it is required that the amount of lateral etching of the deposition oxide film 512 be held low. A simple way of achieving this may be to reduce the thickness of the deposition oxide film 512 to a further extent. The reason is that as the thickness of the deposition oxide film 512 is reduced, the amount of lateral etching of the deposition oxide film 512 decreases. In the above-mentioned conventional technology, however, the deposition oxide film 512 will become further thinner after the formation of the base junction opening portion by means of wet etching. As a result, the effect of the deposition oxide film 512 as an etching stopper will wear off.
Conversely, when the second deposition oxide film 512 is thick, the reduction in size of the width A is great, and there is a limit to the reduction in the width A.